Isolated vertical power device structure with both N-doped and P-doped trenches

ABSTRACT

A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region. Thereafter, a film containing a second type dopant is deposited in the front and back isolation wall trenches. In the conduction region on the back surface, conduction region trenches are formed inside the perimeter of the isolation wall trenches. A first type dopant is deposited in the conduction region trenches. The dopants are diffused from the conduction region trenches and isolation wall trenches to form a first conductivity type conduction region structure and a second conductivity type isolation wall.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to semiconductor devices, andmore particularly to a means and method for providing a vertical powerdevice having an insulating isolation wall for electrically isolatingone device from another, and having a low resistance path to theconduction region of the device.

2. Description of the Prior Art

A vertical power semiconductor is an electronic device used to controlthe flow of electrical power. When a vertical power semiconductor deviceis fabricated in a semiconductor substrate, the device usually requireselectrical isolation from other regions of the substrate. The purpose ofsuch isolation is to separate the vertical power device from othercomponents on the same chip or wafer, or to create an electricallyinactive protection area at the border of the device, where the severaldevices or chips on a wafer may be cut apart from one another.

One solution to the problem of isolating vertical power devices isdescribed in U.S. Pat. No. 6,579,782 (the '782 patent) issued to Roy onJun. 17, 2003, which is hereby incorporated herein by reference. The'782 patent describes a method for manufacturing a four-layer verticalpower component, such as the four-layer thyristor shown in thesimplified cross-sectional view of FIG. 1 herein. A thyristor is anelectronic device used to control the flow of electrical power. It issimilar to a diode, but it has an extra terminal for receiving a signalthat places the device in a conductive state. The thyristor is formed ina silicon semiconductor substrate 20 that is lightly doped with anN-type dopant. It has a four-layer structure consisting of alternatingP-type and N-type materials (e.g., PNPN). The thyristor is surrounded atits external periphery with an isolating wall, which is formed with amaterial of a conductivity type opposite to that of the substrate.

Manufacturing the prior art thyristor begins with the step of forming,on the lower surface 22 of the substrate, a succession of holes 24perpendicular to the surface. Some of the holes—the holes around aperimeter of a conduction region—form a lower portion of an isolationwall. The holes within the perimeter form the conduction region. Next, adopant having a second conductivity type, which is opposite to that ofthe substrate, is diffused from both types of holes. Further stepsinclude: boring similar holes 26 on the upper surface 28 of thesubstrate to define an upper portion of the isolating wall; anddiffusing, from holes 26 a dopant of the second conductivity type with ahigh doping level, wherein the holes 24 and 26 of to the isolating wallare sufficiently close for the diffused areas to join laterally andvertically.

In the prior art, the same type of dopant is diffused from bothisolation wall holes and conduction region holes. This process worksfine for making four-layer devices, but an improved process is neededfor making other devices, such as bipolar transistors and power MOSFETs.Such three-layer devices require isolation walls having a secondconductivity type, and a conduction region having a first conductivitytype.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which likenumbers designate like parts, and in which:

FIG. 1 is a simplified cross-section view of a prior art vertical powerdevice;

FIG. 2 is a high-level flowchart of a first embodiment of a method ofmanufacturing a vertical power device on a semiconductor substrate inaccordance with the method and apparatus of the present invention;

FIG. 3 is a high-level flowchart of a second embodiment of a method ofmanufacturing a vertical power device in accordance with the presentinvention;

FIG. 4 is a high-level flowchart of a third embodiment of a method formanufacturing a vertical power device in accordance with the presentinvention;

FIGS. 5 and 6 are simplified cross-section views of a vertical powerdevice in various stages of manufacturing in accordance with the firstembodiment of the present invention;

FIGS. 7-10 are simplified cross-section views of a vertical power devicein various stages of manufacturing in accordance with the secondembodiment of the present invention;

FIGS. 11-12 are simplified cross-section of views a vertical powerdevice in various stages of manufacturing in accordance with the thirdembodiment of the present invention; and

FIGS. 13-16 are partial views of a back surface of a semiconductorsubstrate showing various examples of structures used in manufacturingthe vertical power device according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The process steps and structures described below may not form a completeprocess flow for manufacturing an integrated circuit device because thepresent invention can be practiced in conjunction with integratedcircuit fabrication techniques currently used in the art. Of thecommonly practiced process steps for manufacturing an integrated circuitdevice, only those steps necessary for an understanding of the presentinvention are described herein. The figures representing cross-sectionviews of portions of an integrated circuit device during fabrication arenot drawn to scale, but are instead drawn to illustrate the importantfeatures and processes of the present invention.

With reference now to the drawings, FIGS. 2-4 illustrate high-levelflowcharts of three embodiments of methods for manufacturing an isolatedvertical power device on a semiconductor substrate in accordance withthe present invention. The devices manufactured by the methods of thepresent invention are three-layer devices consisting of three layers ofalternating P- and N-type material. The types of devices manufacturedaccording to the present invention include bipolar-based devices andMOSFET-based devices. FIGS. 5-16 illustrate corresponding physicalresults of the various steps of these methods. In the description thatfollows, the manufacturing steps are described with reference to aparticular block in a flowchart. Following the description of themanufacturing step is a description of a corresponding figure that bestillustrates the physical results of that flowchart step.

The flowchart in FIG. 2 depicts a first embodiment of a method formanufacturing an isolated vertical power device in a semiconductorsubstrate in accordance with the present invention. As illustrated, theprocess begins at block 100, and thereafter passes to block 102, whereinback isolation wall trenches are formed in a back surface of asemiconductor substrate having a first conductivity type.

This step of forming back isolation wall trenches is illustrated in FIG.5, which shows substrate 40 having back surface 42 and front surface 44.Back isolation wall trenches 46 have been formed in back surface 42.

In the examples of the embodiments illustrated in the figures, thevertical power device is manufactured in an N-type substrate 40, whichmay be referred to herein as a “substrate having a first conductivitytype.” The phrases “first conductivity type” and “second conductivitytype” are used in this description because N- and P-type dopants (andother similarly polarized materials used in semiconductor manufacturing)may be exchanged to make a complimentary device having an oppositepolarity.

Substrate 40 is typically a wafer of semiconductor material, such assilicon, which is large enough for concurrently manufacturing hundredsof similar devices, or hundreds of circuits containing such verticalpower devices. Back isolation wall trenches 46 are arranged to surrounda perimeter of a “conduction region” of the vertical power device. Thisis illustrated in the plan view of FIG. 13, which shows that backisolation wall trench 46 may be a continuous trench on back surface 42of substrate 40, which forms a closed shape around a perimeter ofconduction region 50. The “conduction region,” or “active region,” ofthe vertical power device may be defined as the region extendingvertically through the substrate that is occupied by switchingstructures of the device, which is the region through which switchedpower passes.

Any one of several well known processes may be used to form the backisolation wall trenches. In a preferred embodiment, the trench is formedby a dry etching process, such as “dry plasma etching,” which is wellknown in the art of semiconductor manufacturing. Dry plasma etching is aphysical and chemical etching process that uses reactive ionized gas toremove unprotected portions of a layer of material, such as thesubstrate, to leave an opening, or recess, which may be referred to as a“trench.” The process of etching a trench may be generally referred toas “forming,” “etching,” or “boring” a trench.

Referring back to FIG. 2, the next step in the process is forming frontisolation wall trenches on the front surface of the semiconductorsubstrate, as illustrated in block 104. This step is preferablyimplemented with an etching process similar to that discussed above inreference to block 102. Formation of the front isolation wall trenchesis shown in FIG. 5, where front isolation wall trenches 48 are formed inupper surface 44 of substrate 40. Front isolation wall trenches 48similarly surround the perimeter of conduction region 50.

Note that back isolation wall trenches 46 and front isolation walltrenches 48 in FIG. 5 are formed on opposite sides of substrate 40, andthat each are formed to a depth in substrate 40 that does not overlapthe depth of the other. In other words, if back trench 46 and fronttrench 48 were formed along the same vertical axis, the trench openingswould not meet or connect. Their depths would fall short of producing anopening that passes all the way through substrate 40. Thus, in apreferred embodiment, the sum of the depths of back trench 46 and fronttrench 48 does not exceed the thickness of substrate 40.

The locations of back isolation wall trenches 46 on back surface 42 arepreferably mirrored by front isolation wall trenches 48 on front surface44. (Note that front surface 44 is not shown in a plan view in thefigures.) Thus, the patterns and shapes shown in the figures for backisolation wall trenches 46 are preferably substantially repeated onfront surface 44 of substrate 40 in forming front isolation walltrenches 48.

More than one isolation wall trench may be used to surround conductionregion 50. The reason for using more than one trench is to make surethat the isolation wall trenches do not remove so much silicon that thewafer is weakened, or becomes susceptible to warping. Thus, twocontinuous trenches 46 and 46′ are shown in FIG. 13, where both of thetrenches concentrically surround conduction region 50. In thecross-sectional views of FIGS. 5-12, two isolation wall trenches areshown, wherein they are represented by pairs of inner and outer trencheson both the right and left sides of substrate 40.

After forming back and front isolation wall trenches, the next step inthe process of FIG. 2 is depositing P-type dopant to fill the front andback isolation wall trenches, as depicted in block 106. In theparticular example shown in FIG. 5, P-type material has been depositedto fill back isolation wall trenches 46 and front isolation walltrenches 48. Note that the conductivity type of the dopant used to fillthe isolation wall trenches is the type opposite of the conductivitytype used for the substrate.

Depositing the P-type dopant is preferably implemented with a chemicalvapor deposition technique, which is well known in the art ofsemiconductor processing. The P-type dopant may be one of several knowndopants, including, but not limited to, boron, indium, or aluminum. TheP-type dopant may be present in a dielectric material such as dopedsilicon dioxide, or in a conductive material such as doped poly silicon.

In the present invention, it is important to fill front and backisolation wall trenches 48 and 46 with deposited dopant material.Therefore, the type of deposition selected, and the specific depositionparameters (e.g., time, temperature, etc . . . ), should be based uponthe dimensions of the front and back isolation wall trenches 48 and 46.For example, the smallest dimension across the trench (i.e., the trenchwidth) should be a distance that allows deposited material to completelyfill the trench opening rather than just depositing a layer thatoutlines or coats the sidewalls of the trench. That is, during thedeposition process, the layers being deposited and accumulating onopposing sidewalls must grow together and close any gap, therebycompletely filling the trench.

After depositing the P-type dopant, it may be removed from the substratesurface using either an etch or a polish step, but it does not need tobe removed if the front and back surfaces 44 and 42 are protected frombeing covered by dopant with a layer of material such as silicondioxide. For example, in the processes described herein, insulatinglayers of oxide, or oxide/nitride (which may be referred to in the artas a “sandwich”) may be applied to the front and back surfaces of thesubstrate to aid in forming and otherwise manufacturing the trenches andother features of the vertical power device. Such a sandwich layer, ordielectric layer 58, is shown in FIGS. 7 and 8. Steps described hereinthat describe removing material from the front or back surfaces of thesubstrate are intended to include removing material from dielectriclayer 58, if such a layer is present.

Returning to the process shown in FIG. 2, the next step, which is anoptional step, is diffusing the deposited P-type dopant, as illustratedat block 108. Diffusion is a high-temperature process in which desiredchemicals (e.g., a dopant) on a wafer are distributed within the siliconsubstrate to form a device component. In the present invention, thisoptional diffusion step redistributes the P-type dopant from the frontand back isolation wall trenches to form an isolation wall within theN-type substrate. This step is optional because diffusing the dopant inthe isolation wall trenches may be performed during a diffusion step(step 116) later in the process.

The diffusion process is illustrated in FIG. 5 by diffused regions 52that surround both back isolation wall trenches 46 and front isolationwall trenches 48. Note that diffused regions 52 have merged together, orintersected, vertically, near the deepest or furthest extents oftrenches 46 and 48, which are near the medial plane of substrate 40. Ifsegmented isolation wall trenches are used, the diffused regions willalso merge, or intersect, horizontally. When the process is completed,the intersection of the diffused regions forms a continuous verticaldiffused region 52 that extends from back surface 42 to front surface44, around conduction region 50. If the conditions (e.g., time andtemperature) of the optional diffusion step 108 are not sufficient tocause the diffusion regions 52 to intersect, a second diffusion step atblock 116 may be used to further diffuse material in the isolation walltrenches and close the gaps in the diffusion areas that form theisolation wall.

Referring again to FIG. 2, the next step in the process is formingconduction region trenches on the back surface of the substrate locatedinside a perimeter of the front and back isolation wall trenches, asdepicted at block 110. According to this first embodiment of the presentinvention, conduction region trenches are formed in an etching stepseparate from the etching of the isolation wall trenches so that theconduction region trenches may be filled with a type of dopant that isdifferent from the type of dopant used to fill the isolation walls. Thissecond etching step is preferably implemented using a plasma etchingtechnique, similar to that described above in reference to blocks 102and 104 for forming isolation wall trenches.

The conduction region trenches are trenches used for creating moreheavily doped regions in the vertical power device in the region of thesemiconductor substrate that conducts the electric current that iscontrolled by the vertical power device. For example, the conductionregion trenches on the back surface of the substrate of a MOSFET formthe drain contact structure.

FIG. 6 shows a placement of a plurality of conduction region trenches 54on back surface 42 of substrate 40. In the embodiment depicted in FIG.6, the size, or width, of conduction region trenches 54 may besubstantially the same as that of isolation wall trenches 46 and 48.Alternatively, conduction region trenches 54 may have a size, shape, ordepth that is different from what is used in isolation wall trenches 46and 48.

FIG. 13 shows a plan view of the placement of conduction region trenches54. Conduction region trenches 54 are located within a perimeter of theback (and front) isolation wall trenches 46 and 46′ to form a conductionregion 50.

Returning to FIG. 2, after forming the conduction region trenches,N-type dopant is deposited to fill the conduction region trenches, asillustrated in block 112. This step may be implemented with a depositionprocess, such as vapor phase deposition, which is similar to the processdescribed above in relation to block 106, where dopant is deposited inthe isolation wall trenches. The N-type dopant may be any one of severalknown dopants, including, but not limited to, phosphorous, arsenic, andantimony.

Note that N-type dopant is used to fill conduction region trenches 54 inN-type substrate 40 because the present invention includes a method formanufacturing a three-layer vertical power device, and therefore thedopant filling conduction region trenches 54 has the same polarity ortype as that of substrate 40.

Also notice that the P-type dopant that was previously deposited to fillisolation wall trenches 46 and 48 (see block 106) acts as a barrier tokeep the presently deposited N-type dopant out of the isolation walltrenches.

After depositing the N-type dopant, the next step in the process is toremove the first and second conductivity type dopants from at least partof the front and back surfaces, as depicted at block 114 in FIG. 2.Removing the dopants prevents the diffusion of P- or N-type materialsinto the surfaces of substrate 40. The dopants are preferably removed bya known etching process, such as a wet or a plasma etch, oralternatively, by a polish operation. (Note that the front and backsurfaces of the wafer may have a dielectric layer or dielectric sandwichpresent.)

The N-doped layer can be left on a bare back surface. If it is left, theN-type dopant also dopes the back surface.

The next step in the process is diffusing the dopants, as depicted atblock 116 in FIG. 2. In FIG. 6, diffusions from isolation wall trenches46 and 48 are shown as isolation wall diffused regions 52. Diffusionsfrom conduction region trenches 54 are shown as conduction regiondiffused regions 56.

As mentioned above, this diffusion step may be the only diffusion stepin the process. Or, if an optional diffusion step has already beenperformed, this step 116 will diffuse dopant in conduction regiontrenches 54 and further diffuse dopants in isolation wall trenches 46and 48. In either case, this step will diffuse both the N-type dopant inthe conduction region trenches and the P-type dopant in the isolationwall trenches.

Diffusion step 116 is carried on under conditions (e.g., for a length oftime at a specific temperature) that are sufficient for the isolationwall diffusing regions 52 to extend from the isolation wall trenchesformed on one surface to join or intersect regions diffusing fromtrenches on the opposite surface, and for any diffusing regions inadjacent isolation wall trenches on the same surface to join orintersect horizontally. With regard to diffusion from the conductionregion trenches 54, the diffused regions 56 do not need to join orintersect in order to provide a more heavily doped conductive path tothe back surface of the device.

While there are typically other steps needed to complete the fabricationof a vertical power device, and such additional steps may beinterspersed in the flowchart of FIG. 2, the steps of this firstembodiment of the present invention end at block 118.

With reference now to FIG. 3, there is depicted a high-level flowchartof a second embodiment of method of manufacturing an isolated verticalpower device in accordance with the present invention. As illustrated,the process begins at block 200, and thereafter passes to block 202wherein back isolation wall trenches and wide conduction region trenchesare formed on the back surface of the substrate. In this embodiment,these isolation wall and conductivity region trenches may be formedusing an etching process, such as that described above with reference toblock 102 in FIG. 2.

As shown on the back of substrate 40 in FIG. 7, wide conduction regiontrenches 60 are wider than the isolation wall trenches 46. For example,isolation wall trenches 46 may have a width (i.e., the narrowestdistance across the trench) in the range of 0.5 to 2.5 μm, while thewidth of the wide conduction region trenches is wider, such as in therange of 1.0 to 5.0 μm. Wide conduction region trenches 60 are formedwithin a perimeter of back isolation wall trenches to form theconduction region of the vertical power device. Notice that wideconduction region trenches 60 are wider than both front or backisolation wall trenches 48 and 46. Wide conduction region trenches 60are preferably about twice as wide as back and front isolation walltrenches.

As mentioned above, both isolation wall trenches 46 and wide conductionregion trenches 60 may be formed during the same etching operation. Incomparison to the process of the first embodiment, this eliminates theneed for an etching step (i.e., step 110) that is exclusively forforming the conduction region trenches. Combining steps saves time andreduces the cost of manufacturing the devices.

In the next step in FIG. 3, front isolation wall trenches are formed onthe front surface of the semi-conductor substrate, as illustrated atblock 204. FIG. 7 shows front isolation wall trenches 48 on frontsurface 44 of substrate 40.

The next step in the process of FIG. 3 is depositing P-type dopant tofill front and back isolation wall trenches, and to form a dopant layeron the walls of the wide conduction region trenches, as illustrated atblock 206. This step is preferably implemented with a depositionprocess, such as that used in blocks 106 and 112 of FIG. 2, discussedabove.

The results of this step are shown in FIG. 8, where substrate 40 iscovered on front and back surfaces 44 and 42 by a layer of depositedP-type dopant 62. P-type dopant 62 has also filled front and backisolation wall trenches 48 and 46. It is important to note that wideconduction region trenches 60 are not completely filled with P-typedopant 62, but rather the walls of wide conduction region trenches 60are coated with a layer of P-type dopant 62, leaving an opening 64 intowide conduction region trenches 60.

In the next step of the process, the P-type layer is etched from thefront and back surfaces of the substrate, and from the walls of wideconduction region trenches, as depicted at block 208 in FIG. 3. Thisetching step, which is preferably an isotropic etching process, leavesthe substrate as shown in FIG. 9, with front and back surfaces 44 and 42etched down to the substrate material, with front and back isolationwall trenches 48 and 46 remaining filled with P-type dopant, and withthe layer of P-type dopant etched from the walls of wide conductionregion trenches 60. P-type dopant can be removed from wide conductionregion trenches 60 because wide conduction region trenches 60 are wider,and because the P-type layer of dopant only coats the side walls of thetrenches, leaving an opening 64 so that the etching process can removethe P-type dopant layer.

After removing the P-type layer of dopant, the next step in the processis to deposit N-type dopant to fill the wide conduction region trenches,as illustrated in block 210 of FIG. 3. In this step, an N-type dopant,which is preferably N-doped poly silicon, is deposited using a wellknown deposition process, such as the process disclosed above withreference to block 106 in FIG. 2. The deposited N-type dopant shouldcompletely fill wide conduction region trenches 60.

Next (or following the diffusion step below), the N-type dopant layer isremoved from at least part of the front and back surfaces of thesubstrate, as depicted at block 212. The result of this step is bestillustrated in FIG. 10, wherein wide conduction region trenches 60 arefilled with N-type dopant, and the N-type dopant, has been removed fromback surface 42 and front surface 44. (Note that the front and backsurface of the wafer may have a dielectric layer or dielectric sandwichpresent.)

If some N-type dopant is left on back surface 42 of substrate 40, withno dielectric present, it will dope the horizontal back surface of thewafer N⁺ also.

In the next step, the N- and P-type dopants are diffused in thesubstrate to form the isolation wall and the conduction region, asillustrated in block 214. The affect of this diffusion step is shown inFIG. 10, wherein. conduction region diffused regions 66 extend outwardfrom wide conduction region trenches 60, and wherein diffused regions 52extend outward from isolation wall trenches 46 and 48.

While there are typically other steps needed to complete the fabricationof a vertical power device, and such additional steps may beinterspersed in the flowchart of FIG. 3, the steps of this secondembodiment of the present invention end at block 216.

Referring now to FIG. 4, there is depicted yet another embodiment of thepresent invention for manufacturing a vertical power device on asemi-conductor substrate. As illustrated, the process begins at block300, and thereafter passes to block 302, wherein back isolation walltrenches and wide conduction region trenches are formed on the backsurface of the semi-conductor substrate. This step is similar to step202 in FIG. 3. The results of this step may be seen in FIG. 7, whereinback surface 42 includes back isolation wall trenches 46 and wideconduction region trenches 60.

Next, front isolation wall trenches are formed on the front surface ofthe substrate, as illustrated at block 304. The results of this step maybe seen in FIG. 7 wherein front isolation wall trenches 48 are formed infront surface 44.

In the next step, P-type dopant is deposited to fill front and backisolation wall trenches, and to form a layer on the walls of the wideconduction region trenches, as depicted at block 306. The P-type dopantis preferably P-doped poly silicon. The thickness of this deposition isselected to full narrow isolation wall trenches, an not fill wideconduction region trenches. The results of this step may be seen in FIG.8, wherein narrow front and back isolation wall trenches 48 and 46 arefilled with P-type dopant, and the walls of wide conduction regiontrenches 60 are coated with a layer 62 of P-type dopant, leaving anopening 64 into wide conduction region trenches 60.

In the next step of the process of FIG. 4, N-type dopant is deposited tofill the opening in the wide conduction region trenches, as illustratedat block 308. The N-type dopant is preferably N-doped poly silicon witha dopant concentration greater than the concentration of the P-typedopant used in step 306. The result of this step is shown in FIG. 11,wherein N-type dopant 68 has filled openings 64 (See FIG. 8) so thatwide conduction trenches 60 includes a layer of P-type dopant 62 on thewalls of the trenches, and the remaining portion of wide conductionregion trench 60 is filled with N-type dopant 68. Thus, N-type dopant isdeposited to fill an unfilled portion of the wide conduction regiontrenches that is defined by the exposed outer surface of the layer ofP-type dopant on the walls of the wide conduction region trenches.

The concentration of N-type dopant 68 is greater than the concentrationof P-type dopant 62 so that during diffusion the N-type dopant 68 willmore than compensate for the presence of P-type dopant 62 as the N-typedopant diffuses into the P-type poly silicon dopant and into the singlecrystal silicon of substrate 40.

After depositing the N-type dopant, both the N- and P-type dopants areetched from at least part of the front and back surfaces of thesubstrate, as illustrated at block 310 in FIG. 4. This etching processis preferably a wet or a plasma etching process. The result of this stepis best illustrated in FIG. 12, wherein front and back surfaces 44 and42 are etched free of dopant, isolation wall trenches 46 and 48 remainfilled with P-type dopant, and wide conduction region trenches 60 arefilled with a P-type dopant layer along the walls, and an N-type dopantfilling the remaining portion of the trench. (Note that the front andback surfaces of the wafer may have a dielectric layer or a dielectricsandwich present.)

The next step in the process of FIG. 4 is diffusing the N- and P-typedopants to form the isolation wall and the conduction region, asdepicted at block 312. As shown in FIG. 12, this step creates theisolation wall diffused regions 52 and the conduction region diffusedregions 56. Although wide conduction region trenches 60 contain a layerof P-type dopant 62, diffused regions 56 have an N conductivity typebecause the N-type dopant in the wide trenches 60 has a higherconcentration, and is thus able to overcome the effects of the P-typedopant.

Although there are typically several other steps needed to complete thefabrication of a vertical power device, and such additional steps may beinterspersed in the flowchart of FIG. 3, the steps of this thirdembodiment of the present invention end at block 314.

As noted in the previous process flows, regions of the front or backsurface may be doped either P-type or N-type if the appropriately dopedlayer (or sandwich, if N-type is over P-type) is left in contact withunprotected regions of the wafer.

While in a preferred embodiment, front and back isolation wall trenches46 and 48 are continuous trenches, the trenches need not be continuous.In other embodiments, the trenches may be segmented, or comprise aseries of holes or short segments. The advantage of using segmentedtrenches is that the wafer is stronger, which prevents wafers frombreaking or warping.

Segmented trenches 80 are shown in FIG. 14. FIG. 15 shows an isolationwall trench comprising a series of holes 82. Holes 82 forming theisolation wall may be repeated or staggered around the outside of afirst set of holes so that more than one concentric series of holessurrounds active region 50. When the isolation wall trench is segmented,steps that diffuse dopants from segmented isolation wall trenches shouldbe conducted for times and at temperatures that allow diffusing regionsto join or intersect vertically and laterally to close gaps betweentrenches on the same side of the substrate and on opposite sides of thesubstrate.

FIG. 16, shows an alternative N⁺ conduction region trench 84 that is acombination of a trench in the shape of a rectangular frame that istraversed by three additional trenches extending across the frame.

The processes described above typically use plasma etching to form thetrenches. Another known process that may be used to form a trench is wetetching.

In an alternate embodiment, the depths of the isolation wall trenchescan overlap. Also, the isolation wall trenches may form holes that passall the way through the substrate. If trenches pass through thesubstrate, the process for filling the trenches with dopant must bemodified.

Persons skilled in the art should appreciate that the embodiments of thepresent invention provide isolated vertical power devices, and methodsof making same, where the devices have low resistance paths to the backof the semiconductor substrate, and wherein epitaxial etching is notrequired. The second and third embodiments (see FIGS. 3 and 4) etch boththe isolation wall trenches and the conduction region trenches on theback surface of the wafer at the same time, which saves time and reducesmanufacturing costs. In the third embodiment (see FIG. 4), both excessP- and N-type dopants on the front and back surfaces of the wafer areetched away at the same time, which saves time and reduces manufacturingcosts.

The foregoing description of a preferred embodiment of the invention hasbeen presented for the purpose of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseform disclosed. Obvious modifications or variations are possible inlight of the above teachings. The embodiment was chosen and described toprovide the best illustration of the principles of the invention and itspractical application, and to enable one of ordinary skill in the art toutilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated. All suchmodifications and variations are within the scope of the invention asdetermined by the appended claims when interpreted in accordance withthe breadth to which they are fairly, legally, and equitably entitled.

1. A method for manufacturing an isolated vertical power device in asemiconductor substrate, the method comprising the steps of: forming, ina front surface of the substrate having a first conductivity type, oneor more front isolation wall trenches, wherein the front isolation walltrenches surround a perimeter of a conduction region of the verticalpower device; forming, in a back surface of the substrate, one or moreback isolation wall trenches surrounding the perimeter of the conductionregion of the vertical power device; depositing a film containing adopant of a second conductivity type into the front and back isolationwall trenches; forming, in the conduction region on the back surface ofthe substrate, one or more conduction region trenches, wherein theconduction region trenches are located within a perimeter of the frontand back isolation wall trenches; depositing a film containing a dopantof the first conductivity type into the conduction region trenches; anddiffusing the dopants from the conduction region trenches and from thefront and back isolation wall trenches into the substrate to form aconduction region structure of the first conductivity type and anisolation wall of the second conductivity type.
 2. The method of claim 1further comprising the step of removing films containing the dopants ofthe first and second conductivity types from at least part of the frontand back surfaces of the substrate prior to diffusing the dopants. 3.The method of claim 1, wherein the step of diffusing the dopants fromthe conduction region trenches and from the front and back isolationwall trenches further includes diffusing the dopants from the conductionregion trenches and from the front and back isolation wall trenchesunder conditions that permit a diffused region from a selected frontisolation wall trench to intersect with a diffused region from aselected back isolation wall trench to form an isolation wall of thesecond conductivity type.
 4. The method of claim 1, wherein the steps offorming front and back isolation wall trenches further includes thesteps of forming front and back isolation wall trenches using a plasmaetching process.
 5. The method of claim 1, wherein the step of formingthe one or more conduction region trenches further includes forming oneor more conduction region trenches having widths greater than widths ofthe front and back isolation wall trenches.
 6. The method of claim 1further comprising the step of forming a dielectric layer on the frontand back surfaces of the wafer before forming a front or back isolationwall trench, or a conduction region trench.
 7. A method formanufacturing an isolated vertical power device in a semiconductorsubstrate, the method comprising the steps of: forming, in a frontsurface of the substrate, one or more front isolation wall trenches,wherein the front isolation wall trenches surround a perimeter of aconduction region; forming, in a back surface of the substrate having afirst conductivity type, one or more back isolation wall trenchessurrounding the perimeter of the conduction region of the vertical powerdevice, wherein a width of the front isolation wall trenches issubstantially the same as a width of the back isolation wall trenches;forming, in the back surface of the substrate, one or more wideconduction region trenches located within a perimeter of the backisolation wall trenches, wherein a width of the wide conduction regiontrenches is greater than a width of the back isolation wall trenches;depositing a film containing a dopant of a second conductivity type tofill the front and back isolation wall trenches, and to form a layer onwalls of the wide conduction region trenches; removing the dopant of thesecond conductivity type from the front and back surfaces of the wafer,and from the walls of the wide conduction region trenches; depositing afilm containing a dopant of the first conductivity type to fill the wideconduction region trenches; and diffusing the dopants from theconduction region trenches, and from the front and back isolation walltrenches, into the semiconductor substrate to form a conduction regionstructure of the first conductivity type and an isolation wall of thesecond conductivity type.
 8. The method of claim 7 further including thestep of removing the dopant of the first conductivity type from at leastpart of the front surface and the back surface of the wafer prior todiffusing the dopants.
 9. The method of claim 7, wherein the steps offorming one or more back isolation wall trenches and forming one or morewide conduction region trenches is performed during a single etchingprocess.
 10. The method of claim 7, wherein the steps of forming frontand back isolation wall trenches, and forming conduction region trenchesfurther includes the steps of forming front and back isolation walltrenches, and forming conduction region trenches using a plasma etchingprocess.
 11. The method of claim 7, wherein the step of formingconduction region trenches further includes forming conduction regiontrenches that have a width that is at least two times a width of theback isolation wall trenches.
 12. The method of claim 7, wherein thestep of depositing a dopant of a second conductivity type furtherincludes depositing a dopant of a second conductivity type to form alayer on walls of the wide conduction region trenches and thereby leavean opening into the wide conduction region trenches.
 13. The method ofclaim 7 further comprising the step of forming a dielectric layer on thefront and back surfaces of the wafer before forming a front or backisolation wall trench, or a conduction region trench.
 14. The method ofclaim 13, wherein the step of removing the layer of dopant of the secondconductivity type from the front and back surfaces of the wafer furtherincludes removing the layer of dopant of the second conductivity typefrom the dielectric layer on the front and back surfaces of the wafer.15. A method for manufacturing an isolated vertical power device in asemiconductor substrate, the method comprising the steps of: forming, ina front surface of the substrate, one or more front isolation walltrenches, wherein the front isolation wall trenches surround a perimeterof a conduction region; forming, in a back surface of the substratehaving a first conductivity type, one or more back isolation walltrenches surrounding the perimeter of the conduction region of thevertical power device, wherein a width of the front isolation walltrenches is substantially the same as a width of the back isolation walltrenches; forming, in the back surface of the substrate, one or morewide conduction region trenches located within a perimeter of the backisolation wall trenches, wherein a width of the wide conduction regiontrenches is greater than a width of the back isolation wall trenches;depositing a film containing a dopant of a second conductivity type tofill the front and back isolation wall trenches, and to form a layer onwalls of the wide conduction region trenches; depositing a filmcontaining a dopant of the first conductivity type to fill a portion ofthe wide conduction region trenches defined by the layer of dopant ofthe second conductivity type on the walls of the wide conduction regiontrenches; diffusing the dopants from the conduction region trenches, andfrom the upper and lower isolation wall trenches, into the semiconductorsubstrate to form a conduction region structure of the firstconductivity type and an isolation wall of the second conductivity type.16. The method of claim 15 further including the step of removingdopants of the first and second conductivity types from at least part ofthe front and the back surfaces of the substrate prior to diffusing thedopants.
 17. The method of claim 15, wherein the steps of forming one ormore back isolation wall trenches and forming one or more wideconduction region trenches is performed during a single etching process.18. The method of claim 15, wherein the steps of forming front and backisolation wall trenches, and forming conduction region trenches furtherincludes the steps of forming front and back isolation wall trenches,and forming conduction region trenches using a dry plasma etchingprocess.
 19. The method of claim 15, wherein the step of formingconduction region trenches further includes forming conduction regiontrenches that have a width that is at least two times a width of theback isolation wall trenches.
 20. The method of claim 15, wherein thestep of depositing a dopant of a second conductivity type furtherincludes depositing a dopant of a second conductivity type to form alayer on walls of the wide conduction region trenches and thereby leavean opening into the wide conduction region trenches.
 21. The method ofclaim 15 further comprising the step of forming a dielectric layer onthe front and back surfaces of the wafer before forming a front or backisolation wall trench, or a conduction region trench.
 22. The method ofclaim 21, wherein the step of removing the layer of dopant of the secondconductivity type from the front and back surfaces of the wafer furtherincludes removing the layer of dopant of the second conductivity typefrom the dielectric layer on the front and back surfaces of the wafer.